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Design-Reuse
14 小时
Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
Frontgrade Gaisler has launched its latest radiation-hardened microcontroller, the GR716B. Building on the success of the ...
Design-Reuse
17 小时
World's First CXL 3.1 Multi-Vendor Interoperability Demo Showcases New Memory Possibilities ...
Traditional interconnects have been unable to deliver the bandwidth, latency, and power efficiency needs of hyperscale data ...
Design-Reuse
13 小时
Redefining XPU Memory for AI Data Centers Through Custom HBM4 - Part 2
HBM implementation challenges This is the second in a three-part series from Alphawave Semi on HBM4 and gives insights into ...
Design-Reuse
11 小时
Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It ...
Semiconductor veterans secure $3.7M seed funding to launch a universal RISC-V processor that eliminates the need for ...
Design-Reuse
16 小时
Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times ...
New RISC-V core design with smart memory controller dramatically speeds up calculations and significantly reduces energy ...
Design-Reuse
2 天
TSMC drives A16, 3D process technology
TSMC is looking to introduce its A16 1.6nm process by the end of 2026 with an IEEE standard for its 3Dblox technology.
Design-Reuse
1 天
Cadence Unveils Arm-Based System Chiplet
Cadence has announced a groundbreaking achievement with the development and successful tapeout of its first Arm-based system ...
Design-Reuse
2 天
Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
Designers of aerospace and defense systems know that their applications are mission-critical and demand the highest levels of ...
Design-Reuse
2 天
Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With ...
FlexNoC 5 interconnect IP with physical awareness improves place and route efficiency and reduces interconnect area and power ...
Design-Reuse
4 天
D&R Headline News (Last 14 Days)
Eliyan today announced the successful tape out of its NuLink PHY in a x64 UCIe Advanced Package Module on Samsung Foundry’s SF4X 4nm advanced manufacturing process. Initial silicon for ...
Design-Reuse
2 天
Behind the Scenes - Introducing Xiphera's Board
Xiphera’s board of five includes company’s co-founders and three other people from different backgrounds. The new board is filled with new kind of ...
Design-Reuse
1 天
Streamlining SoC Design with IDS-Integrate™
System-on-chip (SoC) designers face significant challenges when integrating thousands of IP blocks from various vendors, ...
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