Design-Reuse2 年
Guidelines for Verilog-A Compact Model Coding
Reduce the memory footprint. Reduce the simulation time. Verilog-A has the potential to change the paradigm for compact model integration into SPICE like simulators [9]. In spite of performance ...
Design-Reuse27 天
Metric Driven Verification of Reconfigurable Memory Controller IPs Using UVM Methodology ...
The paper presents a method for verifying a standard SDRAM controller IP, based on UVM framework using the Object Oriented verification language System Verilog. The verification technique focuses on a ...